1. Field of the Invention
This invention relates generally to data processing systems and, more particularly, to data processing systems having multiple digital signal processor subsystems exchanging data using a high level data link controller. The high level data link controller processes a plurality of signal groups and transmits the signal groups as a packet of signals. The invention relates to the flow of signal groups from a direct memory access unit to a high level data link controller.
2. Background of the Invention
As the applications to which the digital signal processor has been applied have increased in magnitude and complexity, the need for greater computational power has similarly increased. One response to the requirement of additional computational power has been to provide a plurality of digital signal processor subsystems on a chip. The requirement for additional computational power has also resulted in an increased need for the exchange of signal groups between the plurality of processors and the external components. Several ports have been developed to provide for this signal group exchange. For example, a serial port can be provided that can participate in the exchange of signal groups with other digital signal processors and a host processor. Similarly, a port can be provided that can provide signal group exchange with peripheral units. And a high level data link controller port can be been provided that permits the exchange of packets of signals used in communication applications.
Referring to FIG. 1, a digital signal processor system 1 having a plurality of digital signal processor subsystems 10(1) through 10(N), according to the prior art, is shown. Each digital signal processor subsystem 10(1) includes a central processing unit (digital signal processor core) 101 and a memory unit 103. The central processing unit 101 processes signal groups stored in the memory unit 103 and exchanges signals therewith. The direct memory access unit 105 is coupled to the memory unit 103 and permits the exchange of signals between the memory unit 103 and external components without impact upon the performance of the central processing unit 101. The central processing unit 101 is also coupled to a host port interface unit 115. The host port interface unit 115 enables the central processing unit 101 to communicate with the host processing unit (not shown). Coupled to the direct memory access unit 105 typically are a multi-channel buffered serial port 107, a peripheral component interface unit 109 and high level data link controller unit 111. The multi-channel buffered serial port 107 exchanges signal groups in a serial format with the host computer unit and off-chip devices. The peripheral component interface unit 109 permits the exchange of signals with off-chip peripheral devices. The high level data link controller 111 permits the exchange of packets of signal groups, typically used in communication protocols, with off chip components.
As will be clear from FIG. 1, the subsystems 10(1) through 10(N) operate independently. Thus, a complete set of interface units to exchange signal groups with off chip components must be supplied for each subsystem 10(1) through 10(N) to insure that the operation of each subsystem 10(1) through 10(N) will not be limited. However, the result of provision of a complete set of interface units with each subsystem is an inefficient use of the semiconductor material and components.
A need has been felt for apparatus and an associated method having the feature of reducing component redundancy resulting from the duplication of components of the digital signal processor subsystems. The apparatus and associated method would have the more particular feature of reducing the number of interface components on the chip. It would be yet another feature of the apparatus and associated method that the subsystems on the chip would share interface components. It would be a still further feature of the apparatus and associated method that a single high level data link controller can process and transmit signal packets from a plurality of digital signal processing subsystems. It would be still a further feature of the apparatus and associated method to provide an efficient transfer of packets from the digital signal processing subsystems to the high level data link controller. It would be yet a further feature of the apparatus and associated method to respond to an interruption in the transmission of a signal packet. It would be yet a further feature of the apparatus and associated method to recover from an interruption in the processing and transmission of a signal packet with a minimum impact on the performance of the data processing system.